The present invention relates to semiconductor structures having advantageous high-frequency characteristics and to processes for producing such semiconductor structures.
With increasing operating speeds of integrated circuits, nowadays up to 2 GHz can already be reached at the developmental stage, the influences to which an active component or a conductor path is subjected by neighboring active components or conductors pose more and more problems. Problems arise, in particular, from cross-talk effects created between neighboring signal lines and from propagation delays which can lead to synchronizing errors, signal delays, etc.
Every electric signal line influences its closest environment due to the electromagnetic field lines which are created by the signal line and propagate according to the prevailing potentials. Therefore, when an integrated circuit is designed, it is particularly difficult with respect to the connection lines between active elements to calculate the propagation delays to be expected, since these propagation delays are substantially determined by the capacitive and inductive characteristics of the lines which, in turn, are influenced by the active elements and signal lines arranged near said lines.
An approach to the solution of this problem is the provision of coaxial, i.e. shielded, lines inside the highly integrated circuit. Former solutions have suggested the manufacture of micro-coaxial conductor paths in the wiring planes of integrated circuits in which an inner conductor path is laid through an insulator by means of standard metallizing techniques as well as lithographic methods, and the insulator is sheathed by another metal layer, as is, for instance, described by M. E. Thomas, I. A. Saadat, S. Segigahma, IEEE-90, "VLSI Multilevel Micro-Coaxial Interconnects for High Speed Devices". The disadvantage of such a solution resides in the additionally required masking steps and thus in increased production costs.
Another suggestion deals with the manufacture of a so-called local "ground plane" which is achieved by means of a multi-layer metallizing method (cf. D. S. Gardner, Q. T. Vu, P. J. van Wijnen, T. J. Maloney, D. B. Fraser, IEDM 93 Proceedings, pp. 251-254, 1993).
The so-called "ground plane" is a metallic layer which extends at a small distance and in insulated fashion above the surface of the semiconductor and is grounded. This metal layer substantially determines the capacitive and inductive characteristics for the conductor paths positioned thereabove, and thus the characteristic impedance thereof, so that capacitive and inductive influences by active elements or conductor paths which are located in the respectively close vicinity are negligible.